1. Field of the Invention
The present invention relates to a semiconductor storage device, such as DRAM, and in particular to a semiconductor storage device which exercises the same control for sense amplifiers for the reading and writing operations and which increases the speed of a writing operation.
2. Related Arts
The capacitance and the speed of dynamic random access memory have been increased, and as the increase in the capacitance of the memory has resulted in a concomitant increase in the size of memory cell arrays and also in the size of address decoders, a need exists for a simplified controller for controlling these circuits. In addition, with the increase in the memory speed there has been an attendant improvement in the reading and the writing speeds, and this has tended to lead to the fabrication of separate optimal controllers for each of these operations. The resolution of such a contradictory problem is required in order to satisfy the demands both for a larger capacitance for a semiconductor storage device, and for an improvement in its speed.
FIG. 1 is a partially schematic diagram illustrating a conventional semiconductor storage device. In a memory cell region MCR are provided a cell array 1, which includes a plurality of word lines WL and a plurality of bit line pairs BL intersecting the word lines WL, and a plurality of memory cells (not shown) located at their intersections; and arrays 5 and 6 of sense amplifiers SA, which are connected to the respective bit line pairs. A word line WL is selected and is driven by a word line driver, and the state of the memory cell connected to the selected word line is read to bit line pairs BL, while the potentials at the bit line pairs BL are detected and amplified by the sense amplifiers SA.
The bit line pairs BL are connected via column gates (not shown) to paired data buses DBX and DBZ, and to data bus amplifiers 4. The data bus amplifiers 4 each include a read amplifier for amplifying data read along the data bus DBX/Z and for outputting the resultant data to a main data bus MDBX/Z, and a write amplifier for driving the data bus DBX/Z in accordance with externally supplied write data.
Column gate selection signals CL0Z to CL3Z, which are used for selecting a column gate, are generated by column decoder drivers 3, which is supplied with column selection signals CA0Z to CA3Z obtained by decording column addresses. A timing signal TWLZ for activating the sense amplifiers is produced from a word line selection signal (not shown) which is activated when a predetermined period of time has elapsed following the driving of a selected word line. Upon the receipt of the timing signal TWLZ, a latch enable generator 2 generates latch enable signals (activation signals) LEX and LEZ for activating the sense amplifiers SA. In response to the generation of these latch enable signals, LEX and LEZ, the sense amplifiers SA in the upper and lower sense amplifier arrays 5 and 6 are activated.
When the thus structured semiconductor storage device is shifted from the standby state to the active state, first, row addresses are input and a word line WL is selected, and in response to the timing signal TWLZ that is activated following the elapse of a predetermined time, the sense amplifiers SA are activated. Then, column addresses are supplied, and in accordance with a read command or a write command, the data detected by the sense amplifiers SA are amplified by the data bus amplifiers 4 and read out, or in accordance with externally supplied write data, the write data is transmitted along the bit line pairs and written to memory cells by the data bus amplifiers 4. For a bit line pair which is not selected by the column gate selection signal CL, rewriting to the memory cells is performed at a potential amplified by the sense amplifier SA.
As is described above, during the reading operation, the sense amplifiers SA drive the data bus DB and transmit the data which have been read to the read amplifiers in the data bus amplifiers 4. During the writing operation, in order to invert and write the data stored in the memory cells, the write amplifiers in the data bus amplifiers 4 invert the states of the sense amplifiers SA and drive the potentials on the bit lines to a level corresponding to the data which are to be written. Therefore, the operation performed by the sense amplifier SA connected to a selected bit line pair causes a delay in the writing operation. In addition, a sense amplifier SA connected to an unselected bit line pair must again write the stored data to an unselected memory cell, and the operation of the sense amplifiers SA is necessary when the word line WL is driven.
As means for resolving the delay of the writing operation, it is proposed that the activation of a sense amplifier which is connected to a selected bit line pair be halted during the writing operation. According to this proposal, however, the operation of the sense amplifiers during a reading process must differ from their operation during a writing process. Therefore, a circuit for the generation of operation control signals must be additionally provided and control signals for the activation of individual sense amplifiers must be generated separately. And in addition, the control provided for the sense amplifiers SA of a selected column and for an unselected column must differ.